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Easy way to define wire output multiplexers in Verilog

Discussion in 'Programming/Internet' started by AlfroJang80, Oct 8, 2018.

  1. AlfroJang80

    AlfroJang80 Guest

    For the wire type in Verilog, I know that I can define a multiplexer as follows

    wire a;

    assign a = select ? 1'b0 : 1'b1;


    And for reg's, I can do it as follows

    reg a;
    always @ (select)
    begin
    case(select)
    1'b0: a = 1'b0;
    1'b1: a = 1'b1;
    endcase
    end


    Now my question arises - it's so easy to describe complex multiplexers using regs/always blocks/procedural statements. It seems so tedious to do the same with wires. What if I wanted to describe a very complex multiplexer driving a wire? Would my select? line be huge?

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